How to create state diagram FPGA

Creating a state diagram for FPGA design involves designing a Finite State Machine (FSM), which is often implemented using hardware description languages like VHDL or Verilog. A state diagram is a graphical representation of the FSM's behavior, transitions, and states.

Here’s a step-by-step guide on creating a state diagram and implementing it in an FPGA:

1. Understand the Problem

• Identify the system's behavior and define the states.
• Determine how the system transitions between states based on inputs or conditions.
• Example: A traffic light controller, UART communication controller, or vending machine logic.

2. Define the States

• Break the system operation into distinct states. Each state represents a unique condition or action of the system.
• Example: A simple FSM for a traffic light controller:
• RED → YELLOW → GREEN → YELLOW.

3. Draw the State Diagram

Use tools such as:

• Paper and pencil (for basic diagrams).
• Digital tools: Microsoft Visio, Lucidchart, draw.io, or HDL-specific tools like Xilinx Vivado or Intel Quartus FSM Editor.

Key Elements of a State Diagram:

1. States: Represented as circles (or ovals).
2. Transitions: Represented as arrows between states, triggered by input conditions.
3. Conditions/Inputs: Written on the transition arrows.
4. Actions/Outputs: Optional labels inside or near the states.

Example for a 2-State FSM (ON and OFF):

• States: ON, OFF
• Transitions:
• ON → OFF (if button = 1)
• OFF → ON (if button = 1)

4. Write the State Table (Optional)

A state table translates the state diagram into a tabular format.

5. Code the State Machine in Verilog or VHDL

Convert the state diagram into HDL code.

6. Implement the FSM in HDL

Example 1: Simple FSM in Verilog

Here is an example of a 2-state FSM (ON and OFF states):

verilog

module fsm_example (
    input clk,       // Clock signal
    input rst,       // Reset signal
    input button,    // Input condition
    output reg led   // Output
);

    // Define the states using an enumerated type
    typedef enum logic [1:0] { 
        OFF = 2'b00, 
        ON  = 2'b01 
    } state_type;

    state_type state, next_state; // Current state and next state

    // State transition logic (sequential block)
    always @(posedge clk or posedge rst) begin
        if (rst)
            state <= OFF;       // Reset to OFF state
        else
            state <= next_state; // Transition to next state
    end

    // Next state logic (combinational block)
    always @(*) begin
        case (state)
            OFF: 
                if (button) 
                    next_state = ON; // Go to ON state if button = 1
                else 
                    next_state = OFF;
            ON:  
                if (button) 
                    next_state = OFF; // Go to OFF state if button = 1
                else 
                    next_state = ON;
            default: 
                next_state = OFF;
        endcase
    end

    // Output logic
    always @(*) begin
        case (state)
            OFF: led = 1'b0;  // LED off in OFF state
            ON:  led = 1'b1;  // LED on in ON state
            default: led = 1'b0;
        endcase
    end

endmodule

Example 2: Simple FSM in VHDL

Here’s the same FSM in VHDL:

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm_example is
    Port ( clk    : in  STD_LOGIC;
           rst    : in  STD_LOGIC;
           button : in  STD_LOGIC;
           led    : out STD_LOGIC);
end fsm_example;

architecture Behavioral of fsm_example is
    -- Define the states
    type state_type is (OFF, ON);
    signal state, next_state : state_type;

begin
    -- State transition logic (sequential block)
    process (clk, rst)
    begin
        if (rst = '1') then
            state <= OFF;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    -- Next state logic (combinational block)
    process (state, button)
    begin
        case state is
            when OFF =>
                if button = '1' then
                    next_state <= ON;
                else
                    next_state <= OFF;
                end if;
            when ON =>
                if button = '1' then
                    next_state <= OFF;
                else
                    next_state <= ON;
                end if;
        end case;
    end process;

    -- Output logic
    led <= '1' when state = ON else '0';

end Behavioral;

7. Simulate the FSM

• Use simulation tools like ModelSim, Vivado Simulator, or Quartus Simulation to verify the design.
• Simulate the FSM by applying test inputs and observing the state transitions.

8. Synthesize and Program the FPGA

• Synthesize the design using tools like:
• Vivado (Xilinx FPGAs)
• Quartus Prime (Intel FPGAs)
• Lattice Diamond (Lattice FPGAs)
• Generate the bitstream file.
• Use a JTAG or USB programmer to load the design onto the FPGA.

Summary of Steps:

1. Define the states and inputs.
2. Draw the state diagram (graphically or with tools).
3. Create a state table (optional).
4. Write the FSM code in Verilog or VHDL.
5. Simulate the FSM to verify correctness.
6. Synthesize the design and program the FPGA.

By following these steps, you can create an FSM, represent it with a state diagram, and implement it on an FPGA board.