How to use XADC FPGA?

The XADC (eXtensible Analog-to-Digital Converter) is a feature available in Xilinx FPGAs, such as those in the 7 Series (e.g., Artix-7, Kintex-7, Virtex-7, and Zynq-7000 devices). The XADC allows FPGAs to monitor analog inputs, system voltages, and on-chip temperature using a 12-bit ADC.

Here’s a guide on how to use the XADC in your FPGA design:

1. Understanding the XADC

The XADC block in Xilinx FPGAs supports:

• Analog inputs: Up to 17 external analog inputs (VP/VN and auxiliary channels).
• On-chip sensors:
• Temperature sensor (on-chip junction temperature).
• Voltage monitoring of FPGA power rails (VCCINT, VCCAUX, VCCBRAM).
• 12-bit resolution with up to 1 MSPS (Mega-Samples Per Second).

The XADC operates in two modes:

1. Single-channel mode: Converts one analog input channel at a time.
2. Sequence mode: Scans multiple channels sequentially.

2. Setting Up the XADC in Vivado

Here’s how you configure and use the XADC:

Step 1: Open Vivado and Add XADC IP

1. Launch the Vivado Design Suite.
2. Create a new project for your target FPGA device.
3. Go to the IP Catalog and search for XADC Wizard.
4. Add the XADC IP to your block design or project.

Step 2: Configure the XADC

• In the XADC Wizard configuration window, you can set:
• Input channels: Select external analog inputs (e.g., VP/VN or AUX channels).
• On-chip sensors: Enable temperature and voltage monitoring.
• Operating mode: Choose either Single-channel or Continuous Sequence Mode.
• Alarms: Configure thresholds for temperature or voltage monitoring.

Step 3: Connect Analog Pins

• The XADC has dedicated analog input pins:
• VP/VN: Primary analog input pair (used for differential or single-ended signals).
• AUX channels: Auxiliary analog inputs (AUX0–AUX15).
• Make sure the analog inputs are correctly connected in your hardware. For instance:
• VP and VN are connected for a differential analog input.
• Single-ended analog inputs can be mapped to AUX channels.

Step 4: HDL Design Integration

To use the XADC in your HDL design (VHDL/Verilog):

1. Instantiate the XADC IP core in your code.

Example instantiation in Verilog:

verilog

xadc_wiz_0 my_xadc (
  .di_in(0),           // Digital input (not used here)
  .daddr_in(7'h00),    // Address for the channel
  .den_in(1'b1),       // Enable conversion
  .dwe_in(1'b0),       // Write enable
  .drdy_out(drdy),     // Data ready signal
  .do_out(do_out),     // Digital output (12-bit data)
  .dclk_in(clk),       // Clock signal
  .reset_in(reset),    // Reset signal
  .vp_in(vp),          // VP analog input
  .vn_in(vn)           // VN analog input
);

2. Read ADC output data: Monitor the 12-bit digital output (do_out) of the XADC IP. It represents the converted analog value.

3. Use the clock (dclk_in) to drive the XADC, as it operates synchronously.

Step 5: Simulation and Testing

• Simulate your design in Vivado or other tools to ensure the XADC operates correctly.
• In hardware, use tools like the XADC Test Bench in Vivado to validate the analog inputs and output data.

3. Example Applications

• Temperature Monitoring: Read on-chip temperature to ensure the FPGA does not overheat.
• Voltage Monitoring: Monitor critical FPGA power supplies.
• Analog Sensor Interface: Use the XADC to read analog signals from sensors like thermistors, potentiometers, or external ADC sources.
• Analog Signal Acquisition: Capture signals like audio or low-frequency waveforms.

4. Key Notes

1. The VP/VN pins must not exceed the allowable analog input voltage range: typically 0V to 1.0V (internal reference) or 0V to 3.3V (external reference).
2. Use differential signals where possible for improved accuracy.
3. The XADC requires proper clocking, typically from a 50 MHz clock source.
4. For external analog inputs, ensure signals are within the FPGA’s analog input voltage range.