It has 144 Registers, 48 Universal I/O Pins, six Dedicated Input Pins, four Dedicated Clock Input Pins, and a Global Routing Pool (GRP). The ispLSI 1024 is a High-Density Programmable Logic Device. All of these components are completely interconnected thanks to the GRP. The 5-Volt in-system programmability and in-system diagnostic capabilities of the ispLSI 1024 are featured. It is the first gadget to enable non-volatile logic and interconnect reprogrammability, enabling genuinely reconfigurable systems.
The Generic Logic Block (GLB) is the fundamental unit of logic on the ispLSI 1024 device. According to the ISPLSI1024-60JL Datasheet, the GLBs are marked A0, A1, and C7. The ispLSI 1024 device has a total of 24 GLBs. Each GLB has 18 inputs, an AND/OR/XOR array that is programmable, and four outputs that can be either combinatorial or registered. The GLB receives inputs from the GRP and designated inputs. To enable connections to any other GLB on the system's inputs, all of the GLB outputs are brought back into the GRP.
