High density devices from the ispLSI 2000E, 2000VE, and 2000VL Families implement logic functions like as registers, counters, multiplexers, and complicated state machines to meet the demands of high performance system logic. The ispLSI 2000E, 2000VE, and 2000VL Families offer a wide range of programmable logic solutions to satisfy today's design requirements, with PLD densities ranging from 1,000 to 8,000 gates. Each device includes a number of Generic Logic Blocks (GLBs) created to increase system performance and flexibility. The ideal balance of internal logic and exterior connections is provided by a ratio of registers to I/O cells that is balanced. The entire system is interconnected, allowing up to 80% of the available logic to be used.The ispLSI 2128VE, 2128VL, and ispLSI 2064VE and 2064VL devices are supported by the 2000VE and 2000VL Families, which provide a variety of I/O choices. There are 128- and 64-I/O variants of the ispLSI 2128VE and 2128VL, as well as 64- and 32-I/O versions of the ispLSI 2064VE and 2064VL.
Feature
ispLSI 2000E Family
❑ Industry’s Fastest 5V CPLD
❑ 225 MHz System Performance
❑ 3.5 ns Pin-to-Pin Delay
❑ 5V Programmable Logic Core
❑ ispJTAG In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
❑ User-Selectable 3.3V or 5V I/O
❑ Programmable Open-Drain Outputs
❑ PCI Compatible Outputs
ispLSI 2000VE Family
❑ Industry’s Fastest 3.3V CPLD
❑ 300 MHz System Performance
❑ 3.0 ns Pin-to-Pin Delay
❑ ispJTAG In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
❑ Boundary Scan Test (IEEE 1149.1)
❑ Programmable Open-Drain Outputs
❑ 3.3V/5V Compatible I/O
ispLSI 2000VL Family
❑ Industry’s Fastest 2.5V Family
❑ 180MHz System Performance
❑ 5.0ns Pin-to-Pin Delay
❑ ispJTAG In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
❑ Boundary Scan Test (IEEE 1149.1)
❑ Programmable Open-Drain Outputs
❑ 3.3V Compatible I/O
ispLSI Development Tools
❑ ispLEVER Systems for PC and Lattice
UNIX-Based Design Tools
❑ Tightly Integrated with Leading CAE Vendors’ Tools
❑ Productivity Enhancing Static Timing Analyzer,
Physical Viewer and Explore Tools
❑ VHDL, Verilog-HDL, ABEL, State Machine and
Schematic Entry
❑ Timing and Functional Simulators
❑ Comprehensive ISP Programming Tools
❑ Windows XP, Windows 2000, Windows 98,
Windows NT, Solaris and Hewlett-Packard
UNIX Platforms
