A programmable video bridging device called CrossLink from Lattice Semiconductor supports a number of interfaces and protocols for mobile image sensors and screens. The system is built using 40-nm Lattice mobile FPGA technology. It combines an FPGA's high degree of flexibility with an ASIC's tiny size, low cost, and low power requirements. CrossLink supports a variety of video interfaces, including SLVS200, subLVDS, HiSPi, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, and MIPI DSI. It also supports MIPI DPI, MIPI DBI, CMOS camera and display interfaces. For CrossLink, Lattice Semiconductor offers a variety of pre-engineered intellectual property (IP) modules.
Designers can focus on the distinctive elements of their designs with more freedom when employing these configurable soft core IPs as standardized building blocks, which boosts productivity. Using CrossLink, the Lattice Diamond design software enables the effective implementation of massive complicated designs. Popular logic synthesis programs offer support for synthesis libraries for CrossLink devices. The Diamond tools arrange and route the design in the CrossLink device using the output from the synthesis tool and the limitations from its floor planning tools.
For timing verification, the tools extract the time from the routing and back-annotate it into the design. For the neighboring ISM markets as well as those for smart phones, tablets, wearables, VR, AR, drones, smart homes, and HMI, Interfaces on CrossLink offer a variety of bridging options. The system can accommodate content with high resolution and bandwidth for mobile cameras and screens at 4 UHD and higher.
Features
Ultra-low power
Sleep Mode Support
Normal Operation – From 5 mW to 150 mW
Ultra small footprint packages
36-ball WLCSP (6 mm2)
64-ball ucfBGA (12 mm2)
80-ball ctfBGA (42 mm2)
80-ball ckfBGA (49 mm2)
81-ball csfBGA (20 mm2)
Programmable architecture
5936 LUTs
180 Kb block RAM
47 Kb distributed RAM
Two hardened 4-lane MIPI D-PHY interfaces
Transmit and receive
6 Gb/s per D-PHY interface
Programmable source synchronous I/O
MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx,SLVS200 Rx, HiSPi Rx
Up to 1200 Mb/s per I/O
Four high-speed clock inputs
Programmable CMOS I/O
LVTTL and LVCMOS
3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)
LVCMOS differential outputs
Flexible device configuration
One Time Programmable (OTP) non-volatile configuration memory
Master SPI boot from external flash
Dual image booting supported
I2C programming
SPI programming
TransFR I/O for simple field updates
Enhanced system level support
Reveal logic analyzer
TraceID for system tracking
On-chip hardened I2C block
Applications examples
Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation
Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation
Single MIPI DSI to Single MIPI DSI Repeater
Single MIPI CSI-2 to Single MIPI CSI-2 Repeater
Single MIPI DSI to Dual MIPI DSI Splitter
Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter
MIPI DSI to OpenLDI/FPD-Link/LVDS Translator
OpenLDI/FPD-Link/LVDS to MIPI DSI Translator
MIPI DSI/CSI-2 to CMOS Translator
CMOS to MIPI DSI/CSI-2 Translator
subLVDS to MIPI CSI-2 Translator
