Erasable programmable logic devices (EPLDs) and field programmable gate arrays (FPGAs) are both advantages that are combined in Altera's Flexible Logic Element MatriX (FLEX) series. Because it combines the fine-grained design and large register count features of FPGAs with the high speed and predictable connectivity delays of EPLDs, the FLEX 8000 device family is perfect for a variety of applications. Compact 4-input look-up tables (LUTs) and programmable registers are used in LEs to construct logic. A quick, continuous network of routing resources offers high performance.
For applications like wide-data-path manipulation, data transformation, and digital signal processing (DSP), FLEX 8000 devices offer a substantial number of storage components. These components are a great option for high-speed controllers, coprocessor functions, TTL integration, and bus interfaces. The high-pin-count packages can integrate multiple 32-bit buses into a single device.
Four dedicated inputs for synchronous control signals with huge fan-outs are included in all FLEX 8000 device packages. On the device's edge, there is a register for each I/O pin. These registers offer short clock-to-output speeds as outputs and quick setup times as inputs.
The FLEX 8000 architecture's logic and connectivity are set up using CMOS SRAM components. At system startup, FLEX 8000 devices are configured using data from a system controller, an Altera serial configuration device, or an industry-standard parallel EPROM. The configuration devices EPC1, EPC1213, EPC1064, and EPC1441 from Altera are used to set up FLEX 8000 devices using a serial data stream. Additionally, configuration data may be retrieved from system RAM or kept on an industry-standard configuration device that is 32 K by 8 bits or bigger. A FLEX 8000 device can be reconfigured in-circuit after it has been configured by performing a reset and loading fresh data. Reconfiguration can be done in real-time while the system is running because it takes less than 100 ms.
