The logic array blocks (LABs) found in MAX 3000A devices are made up of groups of 16 macrocells that range in size from 32 to 512. Each macrocell features a configurable register with separately programmable clock, clock enable, clear, and preset capabilities as well as a programmable AND/fixed-OR array. Each macrocell can be enhanced with up to 32 product terms, including shared expander and high-speed parallel expander product terms, in order to construct sophisticated logic functions.
Devices using the MAX 3000A offer configurable speed/power optimization.
The speed-critical parts of a design can operate at high speed and full power while the non-speed-critical parts operate at low speed and low power. With the use of this speed/power optimization tool, the designer can set up one or more macrocells to run at 50% or less power while only adding a small temporal delay. Additionally, MAX 3000A devices have a setting that lowers the output buffers' slew rate, decreasing noise transients during non-speed-critical signal switching. All MAX 3000A devices can be utilized in mixed-voltage systems because all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant and all output drivers can be tuned for 2.5 V or 3.3 V.
Altera development systems, integrated packages that provide schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming, support MAX 3000A devices. For enhanced design entry and simulation support from other industry-standard PC- and UNIX-workstation based EDA tools, the software offers EDIF 2 0 0 and 3 0 0, LPM, VHDL, and Verilog HDL interfaces. The software is compatible with Windows-based computers, Sun SPARCstation workstations, and HP 9000 Series 700/800 workstations.
