Field Programmable System-on-a-Chip (FPSC) logic and an embedded system solution are combined on a single device, adding a completely new dimension to programmable logic. For designers that require the many benefits of FPGA-based design execution along with high-speed serial backplane data transfer, Lattice has created a solution. The ORT8850 family of embedded backplane transceivers (SERDES) operates at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are utilised) and is based on the Series 4 reconfigurable integrated System-on-a-Chip (SoC) architecture.Along with approximately 600K useable FPGA system gates (ORT8850H) and a full-duplex synchronous interface with built-in Clock and Data Recovery (CDR) in standard-cell logic, this is coupled. Designers can create a configurable interface while retaining tried-and-true backplane driver/receiver technology by incorporating protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for HDLC for Internet Protocol (IP). The tool can also be used by designers to facilitate high-speed data transfer between buses that are not SONET/SDH-based in a system. Our PCI soft core, for instance, can be used by designers to create a 6.8 Gbits/s PCI-to-PCI half bridge.
A clockless High-Speed Interface for device-to-device communication on a board or across a backplane is provided by the ORT8850 family. Increased system performance, simpler clock domain design in a multiboard system, and fewer signals on the backplane are all made possible by the ORT8850's integrated clock recovery. The backplane transceiver will be useful to network designers as a network termination device. The backplane transceiver allows programmable logic to terminate the network into proprietary systems, as well as faster SONET framing, pointer movement, and transport overhead handling. All SONET functionality is concealed from the user in non-SONET applications, thus no prior networking knowledge is necessary.
