In place of traditional SSI/MSI gates and flip-flops, the PALCE22V10 offers user-programmable logic at a lower chip count. An improved PAL device called the PALCE22V10Z was created using zero-power, high-speed, electrically erasable CMOS technology. In order to replace traditional zero-power CMOS SSI/MSI gates and flip-flops at a lower chip count, it offers user-programmable logic. The PALCE22V10Z offers high speed and no standby power. The PALCE22V10Z enables prolonged battery-powered operation with a maximum standby current of 30 A. The well-known Boolean logic transfer function, the sum of products, is implemented by the PAL device. A programmable AND array driving a fixed OR array makes up the PAL device. The OR array adds specified words at the outputs, whereas the AND array is configured to generate specific product terms. The outputs of the product terms are distributed differently over the fixed OR array, ranging from 8 to 16 . The output macrocell is fed by the OR sum of the products. Every macrocell has the option of being configured as registered, combinatorial, active-high, or active-low. Two bits control two multiplexers in each macrocell, determining the output configuration.
FUNCTIONAL DESCRIPTION
The systems engineer can use the PALCE22V10 to implement the design on-chip by programming EE cells to set up the device's AND and OR gates to perform the appropriate logic function. Complex interconnections between gates that once required lengthy planning are now moved from the PC board to silicon, where they can be easily changed during prototyping or production. The PALCE22V10Z is the PALCE22V10 in zero-power form. It has all the PALCE22V10's architectural elements. The PALCE22V10Z also features no product term disable and 0% standby power. Product terms linked to both the true and complement of any single input assume the logical LOW state, while product terms with all connections open assume the logical HIGH state. The PALCE22V10 features 10 I/O macrocells and 12 inputs. One of four possible output configurations—registered output, combinatorial I/O, active high, or active low—is supported by the macrocell. The user's design specification and accompanying programming of the configuration bits S0–S1 are taken into consideration while choosing the configuration. A programmable bit connects multiplexer controls to ground (0), choosing the multiplexer's "0" path. By erasing the bit, the control line is disconnected from GND and driven to a high level, choosing the "1" path.
FEATURE
◆ As fast as 5-ns propagation delay and 142.8 MHz fMAX (external)
◆ Low-power EE CMOS
◆ 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
◆ Varied product term distribution allows up to 16 product terms per output for complex functions
◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
◆ Global asynchronous reset and synchronous preset for initialization
◆ Power-up reset for initialization and register preload for testability
◆ Extensive third-party software and programmer support
◆ 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
◆ 5-ns and 7.5-ns versions utilize split leadframes for improved performance
