Virtex-E FPGA family Overview
High-performance, high-capacity programmable logic solutions are provided by the Virtex-E FPGA series. By utilizing an aggressive 6-layer metal 0.18 m CMOS process and optimizing the new design for place-and-route efficiency, significant gains in silicon efficiency are achieved. These developments transform natives to mask-programmed gate arrays, making Virtex-E FPGAs strong and adaptable.
The Virtex-E series is an evolutionary step in programmable logic design, building on knowledge learned from Virtex FPGAs. The Virtex-E family provides a high-speed and high-capacity programmable logic solution that increases design flexibility while decreasing time-to-market by combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology.
Virtex-E Architecture
The changeable logic blocks (CLBs) and programmable input/output blocks (IOBs) that make up Virtex-E devices' flexible, regular architecture are linked by a rich hierarchy of quick, adaptable routing resources. The Virtex-E series can support even the largest and most complicated designs thanks to its ample routing resources.
SRAM-based Virtex-E FPGAs are configured by writing configuration information to internal memory cells. SelectMAP, slave serial, and JTAG modes can all be used to write configuration data into the FPGA or read information from an external SPROM (master serial mode). Complete design support for Virtex-E is provided by the standard Xilinx Foundation Series and Alliance Series Development systems. This support extends to all areas, including behavioral and schematic entry, simulation, automatic design translation and implementation, and the creation and download of a configuration bit stream.
Higher Performance
Performance-wise, Virtex-E devices outperform earlier FPGA versions. Using source synchronous data transmission architectures, designs are capable of synchronous system clock speeds of up to 240 MHz with I/O. The 3.3V PCI standards are fully met by Virtex-E I/Os, and interfaces that run at 33 MHz or 66 MHz can be implemented. Performance varies depending on the design, although several designs can function internally at rates greater than 133 MHz and can even reach above 311 MHz.
