FPGAs on the QPro Virtex-II Pro platform are ideal for designs based on IP cores and unique modules. The PowerPC CPU blocks are incorporated into the family's Virtex-II Pro architecture. Complete solutions for telephony, wireless, networking, video, and DSP applications are enabled by this family of FPGAs.
High performance designs in a variety of densities are made possible by the cutting-edge 0.13 m CMOS nine-layer copper technology and Virtex-II Pro architecture. The QPro Virtex-II Pro series is a potent substitute for mask-programmed gate arrays and boosts programmable logic design capabilities by combining a wide range of customizable features and IP cores.
User-programmable gate arrays with a variety of configurable components and embedded blocks, QPro Virtex-II Pro devices are designed for high-density and high-performance system designs. The following capabilities are implemented by QPro Virtex-II Pro devices:
Blocks of the IBM PowerPC 405 RISC processor.
The interface between package pins and the internal programmable logic is provided by SelectIO-Ultra blocks. The programmable IOBs support the most well-liked and cutting-edge I/O standards.
Basic storage components are included in Configurable Logic Blocks (CLBs), which offer functional components for synchronous and combinatorial logic. Each CLB element's BUFTs (three-state buffers) power specialized segmentable horizontal routing resources.
True Dual-Port RAM's huge 18 Kb storage elements are provided by Block SelectRAM+ memory modules.
18-bit x 18-bit dedicated multipliers make up embedded multiplier blocks.
Digital Clock Manager (DCM) blocks offer selfcalibrating, entirely digital solutions for clock multiplication and division, clock phase shifting at both the coarse and fine grain sizes, and clock distribution delay correction.
