Power Supply Requirements for Power-On
To ensure effective initialization, Xilinx FPGAs need a minimum rated power supply current capacity, and the necessary current is influenced by the power supply ramp-up time. More current is needed for a quick ramp-up than for a gradual one. 50 ms is the longest ramp-up time. A ramp-up time quicker than 2 ms is not specified for current capacity. The current capacity varies linearly with ramp-up time; for example, an XQR4036XL with a ramp-up time of 25 ms would need the amount of current represented by the point on the straight line connecting 1A at 120 s to 500 mA at 50 ms at the 25 ms time mark. This point has a current of about 750 mA.
AC Switching Characteristic of XQR4000XL
The testing procedures outlined in MIL-M-38510/605 are used to mimic testing of the switching parameters. The functionality of every device has been verified. Internal test patterns are used to calculate internal timing parameters. These examples assume that each accessible column has one vertical clock line driven by one global clock input and that the global clock net clocks all available IOB and CLB flip-flops.
The clock distribution is quicker when fewer vertical clock lines are coupled; the delay is greater when several clock lines per column are powered by the same global clock. Utilize the numbers supplied by the static timing analyzer (TRCE in the Xilinx Development System), which are back-annotated to the simulation netlist, for more detailed, more accurate, and worst-case assured data that reflects the actual routing structure. These path delays were taken from the static timing analyzer report and are being offered as guidelines. The worst-case operating circumstances (supply voltage and junction temperature) are assumed for all temporal parameters.
Guidelines for the XQR4000XL CLB Switching Characteristic
Switching parameter testing is modeled after the testing procedures outlined in MIL-M-38510/605. The functionality of every device has been verified. Internal test patterns are used to calculate internal timing parameters. The representative values are listed below. Use the values supplied by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist for more detailed, more accurate, and worst-case assured data. The worst-case operating circumstances (supply voltage and junction temperature) are assumed for all temporal parameters. Unless otherwise specified, values are stated in nanoseconds and apply to all XQR4000XL devices.
