The performance bottlenecks connected with conventional FPGAs are removed by the Speedster7t FPGA family, which is optimized for high-bandwidth workloads. Built on TSMC's 7nm FinFET process, Speedster7t FPGAs feature a revolutionary new 2D network-on-chip (NoC), an array of new machine learning processors (MLPs) optimized for high-bandwidth and artificial intelligence/machine learning (AI/ML) workloads, high-bandwidth GDDR6 interfaces, 400G Ethernet and PCI Express Gen5 ports — all interconnected to deliver ASIC-level performance while retaining the full programmability of FPGAs.
The new, high-performance Speedster 7t FPGA family from Achronix is specifically made to support extremely high bandwidth needs for demanding applications like networking infrastructure and data center workloads. Some of the most demanding processing workloads in the data center are those related to these high-performance applications, particularly those that involve artificial intelligence and machine learning (AI/ML) and high-speed networking.
Several performance criteria characterize these data-center and networking workloads:
The ability to handle high-speed data rates from a host processor’s PCIe port and up to 400 Gbps Ethernet ports.
The ability to store multiple gigabytes of incoming data and to access that data quickly for processing within the FPGA.
The ability to move massive amounts of data among the FPGA’s I/O ports, its internal memory, attached external memory, and its on-chip computing resources.
The ability to process high computational loads with tera-operations-per-second of performance.
The Speedster7t FPGA family can more than satisfy each of these performance criteria with appropriately scaled and optimized on-chip resources.
High-speed data enters an FPGA-based processing node for data center and networking applications in two main ways: through PCIe connections to a host processor and through high-speed Ethernet connections to other data center resources. The PCIe Gen5 interfaces for the host-processor connection(s) and numerous SerDes ports with the ability to support 400 Gbps Ethernet connections are implemented in the Speedster7t family in order to maximize data rates over these connections. For inter- and intra-system data communications used in data centers and a wide range of other FPGA-based applications, both of these I/O standards represent the quickest, most up-to-date specifications. Numerous, high-speed I/O ports on the Speedster7t FPGA support data rates that data centers anticipate experiencing in the near future.
Most FPGAs use on-chip SRAM to store data that needs to be accessed quickly. The Speedster7t FPGA family also includes a significant amount of memory. But even when the FPGA in question is made using 7nm FinFET process technology, the sheer amount of data that must be handled by many data-center applications overwhelms any amount of on-chip SRAM almost invariably.
As a result, the Speedster7t has several GDDR6 graphics SDRAM ports. In the near future, GDDR6 SDRAMs will deliver SDRAM access speeds that are faster than LPDDR5 SDRAM while also having lower DRAM costs (per stored bit). The combination of these features makes GDDR6 SDRAM interfaces the ideal option for developing next-generation system designs. Up to eight separate GDDR6 memory ports are supported by Speedster7t family members.