The third generation of Altera's FPGAs to integrate high-speed serial transceivers with a scalable, high-performance logic array is the Stratix II GX family of devices. Each of the 4 to 20 high-speed transceiver channels in Stratix II GX devices has inherent SERDES capabilities and clock and data recovery unit (CRU) technology, enabling data rates of up to 6.375 gigabits per second (Gbps).
The transceivers are organized into four-channel transceiver blocks and have compact die sizes and low power requirements. Based on the Stratix II architecture, the Stratix II GX FPGA technology provides a 1.2-V logic array with unrivaled performance, versatility, and time-to-market capabilities. Stratix II GX devices are excellent for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications thanks to their scalable, high-performance architecture.
