Intel's 28 nm Stratix V FPGAs deliver the high bandwidth, high level of system integration, and ultimate flexibility for high-end applications.
Optimized for high-performance, high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps.
Optimized for high-performance, variable-precision digital signal processing (DSP) applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps.
Optimized for ASIC prototyping with 952K logic elements on the highest performance logic fabric.
Integrated 28.05- and 14.1-Gbps transceivers, with up to 50 percent lower transceiver power compared to previous-generation devices
Up to 6 x72 DDR3 memory interfaces at 933 MHz
2.5 TMACS of signal processing performance
PCI Express* Gen3, Gen2, and Gen1 hard intellectual property (IP) support
Double the density without a cost and power penalty, through Embedded HardCopy Blocks, which deliver up to 14.3M ASIC gates or up to 1.19M logic elements. The blocks harden standard or logic-intensive functions including interface protocols like PCI Express* Gen3, Gen2, and Gen1, and application-specific functions like 40G/100G/400G
Partial reconfiguration, which enables you to reduce the size of FPGAs, saving board space, cost, and power
Fractional phase-locked loops (fPLLs), which provide increased clocking flexibility and replace on-board voltage-controlled crystal oscillators (VCXOs)
Integrated electronic dispersion compensation (EDC) capability in transceivers, which eliminates the need for external PHY to interface to optical modules
User-friendly fine-grain partial reconfiguration, which allows you to change core functionality on the fly
Dynamically reconfigurable transceivers, which let you easily support multiple protocols, data rates, and physical media attachment (PMA) settings
Configuration via Protocol (CvP) using the existing PCI Express* link in your application, which allows for a less complex board design
Stratix V FPGAs reduce total power by 30 percent compared to previous-generation devices through key technologies:
Programmable Power Technology that maximizes core performance while simultaneously reducing power
TSMC's 28-nm high-K metal gate high-performance process optimized for lower power
0.85-V/0.9-V core voltage
Partial reconfiguration
Embedded HardCopy Blocks and integrated core and transceiver hard IP
