Nine Big Fast Megablocks, or a total of 9 x 120 = 1080 macrocells, make up the ispLSI 81080V device.
The Global Routing Plane has 144 I/O cells in total, and each Big Fast Megablock has a total of 24 I/O cells. This results in (9 x 24) + 144 = 360 I/Os for the full I/O version, and 72 Big Fast Megablock I/Os + 120 global I/Os = 192 I/Os for the partial I/O version.
The device contains a total of 1440 registers, or 1080 macrocells plus 360 I/O cells.
Functional
Ultra-large, high-density in-system programmable LOGIC
- Enhanced pin-locked architecture, symmetrical general-purpose logic blocks connected by hierarchical large fast macroblocks and global routing planes
- Product term sharing array supports up to 28 product terms per macro cell output
- Macrocells support concurrent combining and registration functions
- Embedded tristate bus can be used as an internal tristate bus or as an extension of an external tristate bus
- Macrocells and I/O registers have multiple control options, including set, reset, and clock enable
- I/O pins support programmable bus hold, pull-up, open-drain, and slew rate options
- Independent VCCIO power supply supporting 3.3V or 2.5V input/output logic levels
- I/O cell registers programmable as input registers for fast setup time or output registers for fast clock output time.
