A High Density Programmable Logic Device with 64 and 32 I/O-pin versions is the ispLSI 2064VL. The device has 64 Registers, a Global Routing Pool (GRP), four dedicated input pins, three dedicated clock input pins, two dedicated pins for global OE input. All of these components are completely interconnected thanks to the GRP. Through the Boundary Scan Test Access Port (TAP), the ispLSI 2064VL offers 100% IEEE 1149.1 Boundary Scan Testability and in-system programmability. In order to create completely reconfigurable systems, the ispLSI 2064VL offers non-volatile reprogrammability of the logic as well as the connection.
The Generic Logic Block (GLB) is the fundamental unit of logic on the ispLSI 2064VL device. The gadget ispLSI 2064VL has 16 GLBs in total. Four macrocells make up each GLB. Each GLB has 18 inputs, an AND/OR/Exclusive OR array that is programmable, and four outputs that can be either combinatorial or registered. The GLB receives inputs from the GRP and designated inputs. To enable connections to any GLB on the device, all of the GLB outputs are brought back into the GRP.
The 32-I/O 2064VL has 32 I/O cells compared to 64 I/O cells in the 64-I/O 2064VL. Each I/O cell has a direct connection to an I/O pin and may be configured independently to be a combinatorial input, output, or bi-directional I/O pin with 3-state control, with the output drivers being able to source or sink 4 or 8 mA. For each output, a separate fast or slow output slew rate setting can be configured, reducing output switching noise overall. For mixed-voltage systems, device pins can be securely driven to 3.3V signal levels.
All of the outputs from the GLBs as well as all of the inputs from the bi-directional I/O cells are fed into the GRP. The inputs of the GLBs are given access to all of these signals. To reduce timing skew, delays across the GRP have been equalized.
The dedicated clock pins on the ispLSI 2064VL device are used to choose the clocks. On a GLB basis, three dedicated clock pins (Y0, Y1, and Y2) or an asynchronous clock can be chosen. Any GLB can generate the asynchronous or Product Term clock for its own clock.
