The Generic Logic Blocks (GLBs) of the ispLSI 5000VE Family of In-System Programmable High Density Logic Devices are composed of 32 registered macrocells, and they are connected by a single Global Routing Pool (GRP) structure. The Global Routing Pool (GRP) between the GLBs is driven by outputs from the GLBs. Switching resources are offered so that any number of the device's GLBs may be driven by signals in the Global Routing Pool. This system enables quick, effective connections throughout the entire device.
Each GLB has 32 macrocells, 160 logic product terms, and three additional control product terms in a fully loaded, programmable AND-array. The Global Routing Pool provides 68 inputs to the GLB, with each product term being provided in both true and complement form. A Product Term Sharing Array (PTSA), which permits sharing up to 35 product terms for a single function, receives the 160 product terms organized into 32 sets of five words each. Conversely, the PTSA can be disregarded for tasks involving five or fewer product terms.For shared controls, the three additional product keywords reset, clock, clock enable, and output enable are utilized.
The Global Routing Pool and the device I/O cells can both be driven by the 32 outputs from the GLB. One input from each macrocell output and one input from each I/O pin are present in the global routing pool.
The 3.3V, non-volatile insystem programmability of the ispLSI 5000VE Family allows for the creation of genuinely reconfigurable systems in both the logic and the interconnect structures. The industry standard IEEE 1149.1-compliant Boundary Scan interface is used for programming. The same interface also supports Boundary Scan testing.
