How to Create an SoC (System-on-Chip) on an FPGA?

Time: 2025-04-28 11:11:57View:

Designing an SoC on an FPGA involves integrating a processor core (CPU), memory, peripherals, and custom logic into a single system. Below is a step-by-step guide to building an FPGA-based SoC.

1. Choose Your FPGA & Development Board

FPGA Family	Development Boards	Key Features
Xilinx Zynq	PYNQ-Z1/Z2, ZedBoard	ARM Cortex + FPGA (PS + PL)
Intel Cyclone V SoC	DE10-Nano, DE1-SoC	Dual-core ARM + FPGA (HPS + FPGA)
Lattice ECP5	OrangeCrab, ULX3S	Soft-core CPU (RISC-V)
Xilinx Artix-7	Arty A7, Nexys A7	MicroBlaze or RISC-V

Recommendation:

For beginners: Xilinx PYNQ-Z2 (Python + ARM + FPGA)
For custom RISC-V: Lattice ECP5 (Open-source tools)
For high performance: Intel DE10-Nano (Dual-core ARM + FPGA)

2. Select a Processor Core

A. Hard-Core Processors (Built-in CPU)

Xilinx Zynq: ARM Cortex-A9/A53 (included in Zynq-7000/UltraScale+)
Intel Cyclone V SoC: ARM Cortex-A9 (HPS - Hard Processor System)

B. Soft-Core Processors (FPGA-Implemented CPU)

Processor	Architecture	Tools
MicroBlaze (Xilinx)	32-bit RISC	Vivado
Nios II (Intel)	32-bit RISC	Quartus
RISC-V (VexRiscv, PicoRV32)	Open-source RISC-V	LiteX, SpinalHDL
ARM Cortex-M1/M3 (FPGA-optimized)	ARM Thumb	Keil/FPGA vendor tools

Recommendation:

For Xilinx: MicroBlaze (easy to use)
For Intel: Nios II (Quartus integration)
For open-source: RISC-V (LiteX/SpinalHDL)

3. Design the SoC Architecture

A basic SoC includes:

CPU Core (ARM/RISC-V/MicroBlaze)
Memory (RAM/ROM) (BRAM, DDR3/4 Controller)
Bus Interconnect (AXI, Wishbone, Avalon)
Peripherals (UART, GPIO, SPI, I2C, PWM)
Custom FPGA Logic (Accelerators, DSP blocks)

Example: Xilinx Zynq SoC Block Diagram

[ARM Cortex-A9] ←AXI→ [DDR Controller]  
                   ↳ [UART]  
                   ↳ [GPIO]  
                   ↳ [Custom FPGA IP]

4. Develop the SoC Using FPGA Tools

A. Xilinx Vivado (Zynq/MicroBlaze)

Create a new project → Select FPGA board.
Add Zynq Processing System (PS) or MicroBlaze CPU.
Configure peripherals (DDR, UART, GPIO, AXI Interconnect).
Add custom RTL/IP (AXI-stream, AXI-lite).
Generate Bitstream → Export to Vitis for software.

B. Intel Quartus (Cyclone V SoC/Nios II)

Launch Platform Designer (Qsys).
Add Nios II CPU or enable HPS (ARM Cortex-A9).
Connect peripherals (Avalon-MM, JTAG UART).
Generate HDL & program FPGA.

C. Open-Source Flow (RISC-V + LiteX)

# Install LiteX & FPGA toolchain
pip install litex
# Build SoC for ECP5
litex-boards --target=orangecrab --build

Supports VexRiscv, PicoRV32, and more.

5. Write Firmware for the SoC

A. Bare-Metal C Code (No OS)

#include <stdint.h>#define UART_BASE 0x40000000void uart_putc(char c) {
    *((volatile uint32_t*)UART_BASE) = c;}int main() {
    uart_putc('A'); // Send 'A' over UART
    while(1);}

Compile with GCC (riscv-none-embed-gcc, arm-none-eabi-gcc).

B. Embedded OS (FreeRTOS, Zephyr, Linux)

Zynq/ARM Cortex-A: Run Linux (Petalinux, Yocto).
RISC-V/Nios II: Use FreeRTOS or Zephyr.

6. Debug & Validate the SoC

Logic Analyzer (Sigrok, Saleae) for FPGA signals.
Serial Terminal (PuTTY, minicom) for UART output.
JTAG Debugging (OpenOCD, GDB) for CPU firmware.

7. Example Projects & Resources

SoC Type	Project	Source
Zynq ARM + FPGA	PYNQ Framework	PYNQ.io
RISC-V SoC	LiteX SoC	GitHub: LiteX
Nios II SoC	DE10-Nano Examples	Intel FPGA Wiki
MicroBlaze SoC	Xilinx Embedded	Xilinx Docs

Conclusion

Building an SoC on an FPGA involves:

Choosing an FPGA with a hard/soft CPU (Zynq, Cyclone V, RISC-V).
Designing the SoC architecture (CPU, memory, bus, peripherals).
Using vendor/open-source tools (Vivado, Quartus, LiteX).
Writing firmware (bare-metal C, RTOS, or Linux).

Next Steps:

Try PYNQ (Python + Zynq) for quick prototyping.
Experiment with RISC-V on Lattice ECP5 for open-source SoCs.
Integrate custom accelerators (DSP, AI) into your SoC.