High-fanout PLL-based clock drivers with in-system programmability, the ispClock5510 and ispClock5520 are intended for use in high performance computing and communications applications. When compared to the ispClock5520, the ispClock5510 offers up to 20 single-ended or 10 differential clock outputs, while the latter offers up to 10 single-ended or five differential clock outputs. It is possible to separately configure each pair of outputs to support a different output frequency and I/O standard (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL). Each output also offers independent, programmable termination, slew-rate, and timing skew control. Nonvolatile E2 CMOS memory on-chip houses all configuration data. By offering programmable input and feedback dividers, the PLL and divider systems of the ispClock5500 enable the synthesis of clock frequencies different from those of the reference input. Five post-PLL V-dividers permit the production of five different output frequencies, adding more versatility. Any one of the five V-dividers' output can be used as loop feedback. The only difference between devices in the ispClock5500 family is the quantity of inputs and outputs; all other functionalities are similar across all members of the family.
Features
■ 10MHz to 320MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak(<70ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individualenable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,LVPECL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Internal feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■ Precision Programmable Phase Adjustment (Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL
• Clock A/B selection multiplexer
• Programmable precision termination
■ Four User-programmable Profiles Stored in E2 CMOS Memory
• Supports both test and multiple operating configurations
■ Full JTAG Boundary Scan Test In-System Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages
■ Applications
• Circuit board common clock generation and distribution
• PLL-based frequency generation
• High fan-out clock buffer
