Description
A general-purpose power-supply monitor and sequence controller, the Lattice Power Manager II LA-ispPAC-POWR1014/A includes both in-system programmable logic and in-system programmable analog functionalities that are implemented in non-volatile E2 CMOS technology. 10 independent analog input channels are provided by the LA-ispPAC-POWR1014/A device to monitor up to 10 power supply test points. Two independently programmable comparators are available on each of these input channels to provide the high/low and in-bounds/out-of-bounds (window-compare) monitor functionalities. Additionally, four all-purpose digital inputs are available for various control tasks. The LA-ispPAC-POWR1014/A offers 14 open-drain digital outputs that can be utilized for supervisory and general-purpose logic interface tasks, as well as for regulating DC-DC converters, low-drop-out regulators (LDOs), and optocouplers. It is possible to set up two of these outputs (HVOUT1-HVOUT2) as high-voltage MOSFET drivers. When operating in high-voltage mode, these outputs may deliver up to 8V to drive the gates of n-channel MOSFETs, enabling them to be utilized as high-side power switches that can be programmed to ramp up and ramp down at different rates. The LA-ispPAC-POWR1014/A includes a 24-macrocell CPLD that may be utilized to carry out combinatorial logic operations as well as complicated state machine sequencing for the control of several power supplies. The CPLD array uses the condition of each comparator on each analog input channel as well as the general-purpose digital inputs as inputs, and the CPLD may control any digital output. From 32 milliseconds to two seconds can be added to delays and time-outs via four separately programmable timers. LogiBuilder, a simple-to-learn language built into the PAC-Designer software, is used to program the CPLD. To keep track of the condition of any analog input channel comparators or digital inputs, control sequences are written.The LA-ispPAC-POWR1014A device's I2 C bus or JTAG interface is utilized to monitor the VMON voltage using the on-chip 10-bit A/D converter. The I2 C bus/SMBus interface enables an external microcontroller to operate logic signals IN2 to IN4 and output pins, read back the status of each VMON comparator and PLD output, and measure the voltages attached to the VMON inputs (LA-ispPAC-POWR1014A only). All I2 C registers can be read out during manufacture via the JTAG interface.
Features
Monitor and Control Multiple Power Supplies
• Simultaneously monitors up to 10 power supplies
• Provides up to 14 output control signals
• Programmable digital and analog circuitry
AEC-Q100 Tested and Qualified
Embedded PLD for Sequence Control
• 24-macrocell CPLD implements both statemachines and combinatorial logic functions
Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
Analog Input Monitoring
• 10 independent analog monitor inputs
• Two programmable threshold comparators peranalog input
• Hardware window comparison
• 10-bit ADC for I2C monitoring (LA-ispPACPOWR1014A only)
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or digital output
2-Wire (I2C/SMBus Compatible) Interface
• Comparator status monitor
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Only available with LA-ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to 3.96V
• Automotive temperature range: -40°C to +105°C
• 48-pin TQFP package, lead-free option
Multi-Function JTAG Interface
• In-system programming
• Access to all I2C registers
• Direct input control
