A wide variety of high-density and high-I/O Complex Programmable Logic Devices (CPLDs) are included in the MACH 5 family. Fast speeds at high CPLD densities, low power consumption, and support for extra features like in-system programmability, Boundary Scan testability, and advanced clocking choices are all provided by the fifth-generation MACH architecture. Both 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation are available from the MACH 5 series. MACH 5 devices are produced with pin-to-pin delays as quick as 5.5 ns using E2 CMOS process technologies in cutting-edge ISO 9000 certified fabrication facilities. The PCI Local Bus Specification is adhered to by devices having 5.5, 6.5, 7.5, 10, and 12-ns specifications.
FUNCTIONAL DESCRIPTION
The MACH 5 family includes a wide range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture offers quick speeds at high CPLD densities, low power consumption, and support for extra features including in-system programmability, Boundary Scan testability, and advanced clocking options. The MACH 5 series offers 3.3-V (M5LV-xxx) and 5-V (M5-xxx) operation. Modern ISO 9000 certified manufacturing facilities use the E2 CMOS technology to manufacture MACH 5 devices with pin-to-pin delays as fast as 5.5 ns. Devices with 5.5, 6.5, 7.5, 10, and 12-ns specifications comply with the PCI Local Bus Specification.
FEATURES
◆ High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
◆ Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
◆ Performance features to fit system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
◆ Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
◆ Advanced E2CMOS process provides high performance, cost effective solutions
