It's high performance and high density, including up to 60,000 usable PLD gates with up to 316 I/Os, 300 MHz 16-bit counters, 400 MHz datapaths, and 0.35 m four-layer metal non-volatile CMOS process for the smallest die sizes, are its highlights.
It is also simple to use and has quick development cycles. It has complete pin-out stability, 100% utilization, and 100% routing, in other words. Furthermore, its variable-grain logic cells deliver high efficiency and full utilization. Consequently, its extensive design tools include top-notch Verilog/VHDL synthesis.
The usable PLD gates for the pASIC 3 family of devices range from 4,000 to 60,000. With QuickLogic's "patented ViaLink" technology, pASIC 3 FPGAs are created on a 0.35 m four-layer metal process to offer a rare combination of high performance, high density, low cost, and exceptional ease-of-use.
