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Classic EPLD Family

Classic EPLD Family

Classic EPLD Family

Classic EPLD Family Overview

Sum-of-products logic and a programmable register are used in traditional electronics.A programmable-AND/fixed-OR structure that can implement logic with up to eight product terms is provided by sum-of-products logic. The programmable register can be bypassed for combinatorial operation or independently programmed for D, T, SR, or K flipflop operation. Furthermore, the AND array's input or feedback paths, as well as a global clock, can be used to separately clock each macrocell register. The designer can program output and feedback routes for combinatorial or registered operations in both active-high and active-low modes using Altera's unique programmable I/O architecture. These properties enable the simultaneous implementation of numerous logic operations.

Altera's MAX+PLUS I development system, a single, integrated package that offers schematic, text entry (including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL) and waveform design entry, compilation and logic synthesis, simulation and timing analysis, as well as device programming, supports conventional devices. The MAX+PLUS II software offers further design entry and simulation support from other industry-standard PC- and workstation-based EDA tools via EDIF 2 0 0 and 3 0 0, LPM, VHDLVerilog HDL, and other interfaces. Workstations running Windows, Sun SPARCstation, HP 9000 Series 700/800, and IBM RISCSystem/6000 may all use the MAX+PLUS II software. Additionally, these devices have built-in logic test circuitry that enables function and AC standards to be checked during normal production processes.

Classic EPLD Family Devices

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