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Home > Product > Intel / Altera Corporation > Classic EPLD Family
EP1810JC-30

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EP1810JC-30

Manufacturer:
Altera
Package/Case:
PLCC
RoHS:
Lifecycle:
Stock Resource:
Factory Excess Stock / Franchised Distributor
Datasheet:
Product Categories:
Classic EPLD Family
Description:
high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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EP1810JC-30 Overview

High-speed, low-power logic integration can be accomplished with the help of this EP1810JC-30. The Turbo-only version of Classic devices, which are made using cutting-edge CMOS technology, is described in this data sheet.

The integration of several PAL and GAL-type devices with densities ranging from 300 to 900 useable gates is simple with classic devices, which offer 100% TTL emulation. The Classic family has counter frequencies as high as 100 MHz and pin-to-pin logic delays as low as 10 ns. The ceramic dual in-line package (CerDIP), the plastic dual in-line package (PDIP), the plastic J-lead chip carrier (PLCC), the ceramic J-lead chip carrier (LCC), the pin-grid array (PGA), and the small-outline integrated circuit (SOIC) packages are only a few of the different packaging options for classic devices.

EP1810JC-30 Specifications

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

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