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Home > Product > Intel / Altera Corporation > Classic EPLD Family

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Classic EPLD Family
Classic EPLD Family Integrated Circuits (ICs) Embedded FPGAs SMD or Through Hole 484-FBGA
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EP1810C-20 Overview

High-speed, low-power logic integration can be accomplished with the help of this EP1810C-20 device. The Turbo-only version of Classic devices, which are made using cutting-edge CMOS technology, is described in this data sheet. The integration of several PAL and GAL-type devices with densities ranging from 300 to 900 useable gates is simple with classic devices, which offer 100% TTL emulation. EP1810C-20 has counter frequencies as high as 100 MHz and pin-to-pin logic delays as low as 10 ns. The ceramic dual in-line package (CerDIP), the plastic dual in-line package (PDIP), the plastic J-lead chip carrier (PLCC), the ceramic J-lead chip carrier (LCC), the pin-grid array (PGA), and the small-outline integrated circuit (SOIC) packages are only a few of the different packaging options for classic devices.

EP1810C-20 comes in windowed packaging and are 100% generically tested gadgets that can be readily modified with the use of ultraviolet (UV) light. Sum-of-products logic and a programmable register are used in traditional electronics.A programmable-AND/fixed-OR structure that can implement logic with up to eight product terms is provided by sum-of-products logic. The programmable register can be bypassed for combinatorial operation or independently programmed for D, T, SR, or JK flipflop operation. Furthermore, the AND array's input or feedback paths, as well as a global clock, can be used to separately clock each macrocell register. The designer can program output and feedback routes for combinatorial or registered operations in both active-high and active-low modes using Altera's unique programmable I/O architecture. These properties enable the simultaneous implementation of numerous logic operations.


EP1810C-20 Features

  • Non-volatile EPROM configuration elements for device erasure and reprogramming

  • Counter frequencies as high as 100 MHz and quick pin-to-pin logic latency as low as 10 ns

  • Pin-grid array (PGA), small-outline integrated circuit (SOIC), dual in-line package (DIP), and plastic J-lead chip carrier (PLCC) packaging are all available with 24 to 68 pins.

  • Programmable security bit to safeguard exclusive designschecked universally to ensure 100% programming yield

  • D, T, JK, and SR flipflops have distinct clear and clock controllers thanks to programmable registers.

  • Support for software development on Windows-based PCs using the Altera MAX+PLUS development system, as well as Sun SPARC stations, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and other third-party development systems.

  • Support for programming using the Master Programming Unit (MPU) from Altera; programming equipment from Data I/O, BP Microsystems, and other outside vendors


EP1810C-20 Applications

  • Medical Endoscope

  • Small Cell Baseband

  • Professional Cameras

  • Machine Vision

  • Carrier Ethernet Backhaul

  • Multi-function Printers

  • Multi-Axis Motor Control

  • Machine Vision

  • Programmable Logic Controller

EP1810C-20 Specifications

CategoryIntegrated Circuits (ICs) Embedded FPGAs
MfrIntel / Altera
SeriesClassic EPLD Family
Mounting TypeSMD or Through Hole
Product StatusActive
Programmable TypeNot Verified
Base Product NumberEP1810C
Operating Temperature-40°C ~ 100°C (TJ)
Supplier Device Package484-FBGA (23x23)

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment


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