The EP610's functional and fuse map equivalent is the general-purpose PAL device known as the PALCE610. Up to 20 inputs and 16 outputs can be used for logic functions. There are 16 I/O macrocells that can each be customized according to the needs of the user. The configuration of the macrocells can be either registered or combinatorial. It is possible to set up the registers as D, T, J-K, or S-R flip-flops. The well-known sum-of-products logic with programmable-AND and fixed-OR structure is used by the PALCE610. Each macrocell receives eight product terms to give logic implementations. The PALCE610 has a low power consumption due to the use of cutting-edge CMOS EE manufacturing technology. Additionally, it is a fast device with a worst-case tPD of 15 ns. There are also 28-pin PLCC and space-saving 24-pin SKINNYDIP packages. This device's rapid erase and reprogram capabilities make prototyping simple. The security bit can be used to prevent copying of a proprietary design once a device has been programmed.
FUNCTIONAL DESCRIPTION
A general-purpose programmable logic device is the PALCE610. There are 16 independently programmable macrocells in it. Each macrocell has a combinatorial or registered configuration option. Flip-flops of the D, T, J-K, or S-R types may be used as registers. The gadget features 2 clock pins and 4 specialized input pins. The 16 macrocells are controlled by 8 clock pins each. A fixed OR logic array is driven by a programmable AND logic array that is implemented in the programming matrix. In order to provide user-programmable input polarity, buffers for device inputs include complimentary outputs. Unused input pins ought to be connected to ground or VCC. Our electrically erasable technology is used in the array. Both a programmable bit and an unprogrammed bit are coupled. Product terms with both the TRUE and Complement bits programmed assume the logical-LOW state, while product terms with all bits unprogrammed assume the logical-HIGH state. The user's design specifications, which can be in a variety of formats, are automatically adjusted to the PALCE610's programmable features. Development software processes the design specification to validate the design and generate a programming file. Once downloaded to the programmer, this file configures the design for the desired function of the user.
FEATURE
■ Lattice/Vantis Programmable Array Logic (PAL) architecture
■ Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed
— -15 = 15-ns tPD
— -25 = 25-ns tPD
■ Sixteen macrocells with configurable I/O architecture
■ Registered or combinatorial operation
■ Registers programmable as D, T, J-K, or S-R
■ Asynchronous clocking via product term or bank register clocking from external pins
■ Register preload for testability
■ Power-up reset for initialization
■ Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages
■ Fully tested for 100% programming yield and high reliability
■ Extensive third-party software and programmer support through FusionPLD partners
