The QL2009 is a member of the pASIC 2 family of FPGAs and has 9,000 usable ASIC gates and 16,000 usable PLD gates. With pASIC 2 FPGAs, you get high speed, high usable density, low cost, and flexibility in the same device thanks to a special combination of architecture, technology, and software tools. For designs described using HDLs like Verilog and VHDL, as well as schematics, pASIC 2 devices are an effective and high performance silicon solution.
There are 672 logic cells in the QL2009. The QL2009 comes in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages and has a maximum of 225 I/Os.
Three fundamental packages offer software support for all of the pASIC families, including the QL2009. The most comprehensive FPGA software solution, from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation, is offered by the turnkey QuickWorks package. For designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation, the QuickToolsTM and QuickChipTM packages offer a solution.
