Devices in the Arria GX family provide 3.125 Gbps serial transceivers, dependable packaging, and an established logic array. Each of the 4 to 12 high-speed transceiver channels in an Arria GX device features clock data recovery (CDR) technology and embedded SERDES circuitry that support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols. Additionally, using the device's Basic mode, users can create custom, serial-based IP. The Stratix II GX family's success is built upon by the transceivers. The 1.2-V logic array provided by the Arria GX FPGA technology has the performance and durability required to support several widely used protocols.
The Arria GX device family expands on the success of the Stratix II GX device family by integrating up to 12 high-speed serial transceiver channels. On the right side of the device, full-duplex (transmitter and receiver) four-channel groups known as transceiver blocks are how Arria GX transceivers are organized. Each block's transceivers are autonomous and have their own set of dividers. Each transceiver can therefore operate at a separate frequency. Each block can choose from two reference clocks, giving each transceiver a choice of two clock domains.
