EP1AGX50CF484C5N provides 3.125 Gbps serial transceivers, dependable packaging, and an established logic array. Each of the 4 to 12 high-speed transceiver channels in this EP1AGX50CF484C5N features clock data recovery (CDR) technology and embedded SERDES circuitry that support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols. Additionally, using the device's Basic mode, users can create custom, serial-based IP. The Stratix II GX family's success is built upon by the transceivers. The 1.2-V logic array provided by the Arria GX FPGA technology has the performance and durability required to support several widely used protocols.
EP1AGX50CF484C5N expands on the success of the Stratix II GX device family by integrating up to 12 high-speed serial transceiver channels. On the right side of the device, full-duplex (transmitter and receiver) four-channel groups known as transceiver blocks are how Arria GX transceivers are organized. Each block's transceivers are autonomous and have their own set of dividers. Each transceiver can therefore operate at a separate frequency. Each block can choose from two reference clocks, giving each transceiver a choice of two clock domains.
| Specification | Value |
|---|---|
| Series | Arria GX |
| Number of Logic Blocks | 2508 |
| Number of I/Os | 229 |
| Maximum Operating Frequency | 622.08 MHz |
| Operating Supply Voltage | 1.2 V to 3.3 V |
| Maximum Operating Temperature | + 70 C |
| Mounting Style | SMD/SMT |
| Package / Case | FBGA-484 |
| Distributed RAM | 2.4 Mbit |
| Minimum Operating Temperature | 0 C |
| Operating Supply Current | 0.5 A |
| Packaging | Tray |
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