A SuperFAST CPLD solution is provided by the high performance ispMACH 4000 series from Lattice. The ispLSI 2000 and ispMACH 4A architectures from Lattice are combined to create the family. The ispMACH 4000 architecture emphasizes important advances to combine the highest performance with low power in a flexible CPLD family while retaining the benefits of both families. High speed, low power, and the flexibility required for simple design are all combined in the ispMACH 4000. This family provides outstanding temporal predictability, routing, pin-out retention, and density migration because to its strong Global Routing Pool and Output Routing Pool.The ispMACH 4000 family offers macrocell densities that range from 32 to 512. In Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Fine Pitch Thin BGA (ftBGA) packages, there are several density-I/O combinations with a range of 44 to 256 pins/balls. The macrocell, package, and I/O options are displayed in Table 1 together with other important variables. The system integration capabilities of the ispMACH 4000 family have been improved. It works with 3.3 V, 2.5 V, and 1.8 V interface voltages as well as 3.3 V, 2.5 V, and 1.8 V supply voltages (4000V, 4000B, and 4000C/Z). When an I/O bank is set up for 3.3 V operation, inputs can be securely driven up to 5.5 V, making this family 5 V tolerant. Slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs, and hot socketing are additional advanced I/O features offered by the ispMACH 4000. The IEEE Standard 1532 interface allows for in-system programming of the 3.3 V, 2.5 V, and 1.8 V ispMACH 4000 family members. Product testing on automated test equipment is also possible thanks to IEEE Standard 1149.1 boundary scan testing capability. The logic core (VCC) is used as the reference for the 1532 interface signals TCK, TMS, TDI, and TDO.
Features
High Performance
• fMAX = 400 MHz maximum operating frequency
• tPD = 2.5 ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output
Ease of Design
• Enhanced macrocells with individual clock,reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT path
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)
• Typical static current 10 µA (4032Z)
• Typical static current 1.3 mA (4000C)
• 1.8 V core low dynamic power
• ispMACH 4000Z operational down to 1.6 V VCC
Broad Device Offering
• Multiple temperature range support
– Commercial: 0 to 90 °C junction (Tj)
– Industrial: –40 to 105 °C junction (Tj)
– Extended: –40 to 130 °C junction (Tj)
• For AEC-Q100 compliant devices, refer to
LA-ispMACH 4000V/Z Automotive Data Sheet
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3 V, 2.5 V or 1.8 V LVCMOS I/O
• Operation with 3.3 V (4000V), 2.5 V (4000B) or1.8 V (4000C/Z) supplies
• 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3 V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3 V/2.5 V/1.8 V In-System Programmable (ISP) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options
