The third-generation MAX architecture from Altera serves as the foundation for the MAX 9000 family of in-system programmable, high-density, high-performance EPLDs. The EEPROM-based MAX 9000 family, which is constructed using cutting-edge CMOS technology, has 6,000–12,000 useable gates, pin-to-pin delays as quick as 10 ns, and counter rates as high as 144 MHz.
