Based on Altera's third-generation MAX architecture, the EPC2LC20NU of in-system programmable, high-density, high-performance EPLDs is designed. EPC2LC20NU, which is constructed using cutting-edge CMOS technology, offers 6,000–12,000 useable gates, pin–to–pin delays as quick as 10 ns, and counter rates as high as 144 MHz.
Programmable logic devices (PLDs) with high performance are based on the third-generation Multiple Array MatriX (MAX) design.
| Specification | Value |
|---|---|
| Memory Type | Flash |
| Memory Size | 1.6 Mbit |
| Operating Frequency | 10 MHz |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 3 V |
| Supply Current | 50 uA |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Mounting Style | SMD/SMT |
| Package / Case | TQFP-32 |
| Packaging | Tray |
| Series | EPC2 |
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