EPC2LI20NGA

EPC2LI20NGA Overview

Based on Altera's third-generation MAX architecture, the EPC2LI20NGA of in-system programmable, high-density, high-performance EPLDs is designed. EPC2LI20NGA, which is constructed using cutting-edge CMOS technology, offers 6,000–12,000 useable gates, pin–to–pin delays as quick as 10 ns, and counter rates as high as 144 MHz. Programmable logic devices (PLDs) with high performance are based on the third-generation Multiple Array MatriX (MAX) design.

The 1.5-V, 0.13-m, all-layer copper SRAM process used in the EPC2LI20NGA allows for densities of up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. EPC2LI20NGA is a low-cost solution for data-path applications with features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements.For connecting to and supporting ASSP and ASIC devices, EPC2LI20NGA supports a number of I/O standards, such as LVDS at data rates up to 640 megabits per second (Mbps) and PCI at 66 and 33 MHz, 64 and 32 bits.

EPC2LI20NGA Features

• High-speed (640 Mbps) LVDS I/O support

• Low-speed (311 Mbps) LVDS I/O support

• 311-Mbps RSDS I/O support

• Up to two PLLs per device provide clock multiplication and phase shifting

• Up to eight global clock lines with six clock resources available per logic array block (LAB) row

• Support for external memory

EPC2LI20NGA Applications

• Medical diagnostics and imaging

• Industrial motor control, industrial networking, and machine vision

• IP and Smart camera

• Video and night vision equipment

• LTE radio and baseband

• Multifunction printers

EPC2LI20NGA Specifications