Based on Altera's third-generation MAX architecture, the EPC112132C20 of in-system programmable, high-density, high-performance EPLDs is designed. EPC112132C20, which is constructed using cutting-edge CMOS technology, offers 6,000–12,000 useable gates, pin–to–pin delays as quick as 10 ns, and counter rates as high as 144 MHz.
Programmable logic devices (PLDs) with high performance are based on the third-generation Multiple Array MatriX (MAX) design.
| Specification | Value |
|---|---|
| Memory Type | Flash |
| Memory Size | 64 kbit |
| Operating Frequency | 6 MHz |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 4.75 V |
| Supply Current | 100 uA |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Mounting Style | SMD/SMT |
| Package / Case | PLCC-20 |
| Packaging | Tube |
| Series | FLEX |
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