Based on Altera's third-generation MAX architecture, the EPC2LC20EM of in-system programmable, high-density, high-performance EPLDs is designed. EPC2LC20EM, which is constructed using cutting-edge CMOS technology, offers 6,000–12,000 useable gates, pin–to–pin delays as quick as 10 ns, and counter rates as high as 144 MHz.
Programmable logic devices (PLDs) with high performance are based on the third-generation Multiple Array MatriX (MAX) design.
| Specification | Value |
|---|---|
| Standard Package | 1 |
| Category | Integrated Circuits (ICs) |
| Family | Embedded - FPGAs (Field Programmable Gate Array) |
| Series | * |
| Packaging | Tray |
| Part Status | Obsolete |
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