The most recent enhanced configuration (EPC) device flash memory standard with a robust configuration controller is described in this paper. You can take use of a number of novel and cutting-edge features that drastically shorten configuration times with a single-chip configuration solution. This document talks about how the concurrent and dynamic configuration, data compression, clock division, and external flash memory interface of EPC devices are implemented in hardware and software.
On the DATA lines, configuration information is sent from the EPC device to the SRAM-based device. The DATA lines are inputs to the SRAM-based devices and outputs on EPC4QC1C00N device. These DATA lines match the Bitn lines in the Altera Quartus II software's Convert Programming Files window. For instance, if you tell the Quartus II software to utilize an SRAM Object File (.sof) for Bit0, that.sof is sent from the EPC device to the SRAM-based device on the DATA line.
| Specification | Value |
|---|---|
| Memory Type | Flash |
| Memory Size | 4 Mbit |
| Operating Frequency | 66 MHz |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
| Supply Current | 50 uA |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Mounting Style | SMD/SMT |
| Package / Case | PQFP-100 |
| Packaging | Tray |
| Series | EPC4 |
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