ISPPAC-CLK5610V-0

ISPPAC-CLK5610V-0 Overview

High-fanout PLL-based clock drivers with in-system programmability, the ISPPAC-CLK5610V-0 is intended for use in high performance computing and communications applications. When compared to the ispClock5620, the ispClock5610 offers up to 20 single-ended or 10 differential clock outputs, while the latter offers up to 10 single-ended or five differential clock outputs. It is possible to separately configure each pair of outputs to support a different output frequency and I/O standard (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL). Each output also offers independent, programmable termination, slew-rate, and timing skew control. Nonvolatile E2 CMOS memory on-chip houses all configuration data. By offering programmable input and feedback dividers, the PLL and divider systems of the ISPPAC-CLK5610V-0 enables the synthesis of clock frequencies different from those of the reference input. Five post-PLL V-dividers permit the production of five different output frequencies, adding more versatility. The output of any of the five V-dividers may be used internally as loop feedback, or the FBKA+/- or FBKB+/- pins may be used externally. The primary variations between devices in the ISPPAC-CLK5610V-0 are just the quantity of inputs and outputs, as shown in the accompanying table. All family members have the same fundamental functionality.

ISPPAC-CLK5610V-0 Specifications