LC51024VG-75F484C

LC51024VG-75F484C Overview

The third iteration of Lattice's SuperWIDE CPLD architecture is the LC51024VG-75F484C. These devices greatly outperform architectures with fewer inputs in terms of speed for common designs thanks to their large 68-input blocks.

By combining a novel product term architecture with a two-tiered hierarchical routing architecture, the LC51024VG-75F484C expands the special advantages of the SuperWIDE architecture to larger densities known as SuperBIG. To enhance system-level performance and integration, sysCLOCK and sysIO capabilities have also been implemented.

​Multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) are joined via a tiered routing system to form the LC51024VG-75F484C. With the use of the Global Routing Pool (GRP), segments are linked together. With the use of routing pools and GLBs, designers may build complex designs on a single device without sacrificing speed.

Each GLB has 163 product keywords and 68 inputs from the SRP. These product terms aggregate together into five product term clusters, which directly feed the macrocell or the PT sharing array. The product term expanders and PT Sharing Array of the LC51024VG-75F484C allow up to 160 product terms to be attached to a single macrocell.

The macrocell can choose between global, product term, and block-level resources and is designed to offer configurable clocking and control functions. The switch matrices and, if necessary, the sysIO cell receive the outputs from the macrocells.

LC51024VG-75F484C Specifications