LCMXO2-256HC-6SG32CAIC

LCMXO2-256HC-6SG32CAIC Overview

Six devices in the LCMXO2-256HC-6SG32CAIC of ultra-low power, instant-on, non-volatile PLDs range in Look-Up Table (LUT) density from 256 to 6864. These devices include hardened versions of frequently used features like the SPI controller, I2C controller, and timer/counter in addition to LUT-based, low-cost programmable logic. Other features include embedded block RAM (EBR), distributed RAM, user flash memory (UFM), phase-locked loops (PLLs), pre-engineered source synchronous I/O support, and advanced configuration support, including dual-boot capability. These properties enable the use of these devices in consumer and system applications that are low-cost and high-volume. The LCMXO2-256HC-6SG32CAIC is created using a non-volatile low-power technology with a 65nm pitch. The architecture of the device includes programmable low swing differential I/Os, as well as the ability to dynamically disable I/O banks, on-chip PLLs, and oscillators. All family members will experience low static power thanks to these capabilities that regulate static and dynamic power consumption.LCMXO2-256HC-6SG32CAIC comes in three varieties: ZE, HC, and HE, which stand for ultra-low power and high performance, respectively. The three-speed classes for the ultra-low power devices are -1, -2, and -3, with -3 being the quickest. The device's architecture enables dynamic disabling of oscillators, on-chip PLLs, and low swing differential I/Os in addition to programmable low swing differential I/Os. These skills to control static and dynamic power usage will result in low static power for the entire family. ZE, HC, and HE, which stand for ultra-low power and high performance, respectively, are the three different types of MachXO2 devices. The ultra-low power devices fall into the -1, -2, and -3 three-speed classes, with -3 being the fastest.

LCMXO2-256HC-6SG32CAIC Specifications