The Generic Logic Blocks (GLBs) of the QL2P150-7PUN121C of In-System Programmable High Density Logic Devices are composed of 32 registered macrocells, and they are connected by a single Global Routing Pool (GRP) structure. The Global Routing Pool (GRP) between the GLBs is driven by outputs from the GLBs. Switching resources are offered so that any number of the device's GLBs may be driven by signals in the Global Routing Pool. This system enables quick, effective Embedded SRAM and Low Power Programmable Fabric are combined. The QL2P150-7PUN121C is made using a six layer, metal CMOS process with a 0.18 m thickness. The voltage at the core is 1.5 or 1.8 V. The output drive and I/O voltage input tolerance can be set to 1.8 V, 2.5 V, or 3.3 V. One register, multiplexer-based logic cell makes up the QL2P150-7PUN121C structure. It is built for multiple, simultaneous output functions and a wide fan-in. The cell has four outputs, a high fan-in, up to 24 simultaneous inputs (including register control lines), and fits a variety of functions (three combinatorial and one registered). Numerous user functions can be accommodated with a single level of logic delay thanks to the high logic capacity and fan-in of the logic cell.
Buy QL2P150-7PUN121C QuickLogic, Get familiar with the QL2P150-7PUN121C PolarPro II Family at VEKEMO...
