The XA2C64A-7VQG44Q is developed for both low power and high performance applications. High-end communication devices can benefit from power savings, and battery-operated devices can benefit from high speed. Overall system reliability is increased by the dynamic operation and low power stand-by. Two Function Blocks are joined via a low power Advanced Interconnect Matrix (AIM) in this device. Each Function Block receives 40 true and complement inputs from the AIM. The Function Blocks are made up of 16 macrocells with several configuration bits that enable combinational or registered modes of operation, together with a 40 by 56 P-term PLA.
These registers can also be configured as a D or T flip-flop or a D latch, and they can be globally reset or preset. Additionally, there are numerous clock signals that can be defined for each macrocell, including both global and local product term types. Slew rate restriction, bus hold, pull-up, open drain, and programmable grounds are examples of output pin designs. Each input pin has a Schmitt trigger input accessible. The macrocell registers can be set up as "direct input" registers to record signals directly from input pins in addition to storing macrocell output states.
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