In a single CPLD, Xilinx XC2C256-7PQ208I combines the incredibly low power adaptability of the XPLA3 family with the high speed and simplicity of use associated with the XC9500/XL/XV CPLD family. This implies that, with the extra benefit of in-system programming, the exact same components can be used for high-speed data communications/computing systems and cutting-edge portable devices. One family that is simple to use and economical combines high-speed operation with low power consumption. The users' power budget is increased through clocking strategies and other power-saving measures. Starting with the Xilinx ISE 4.1i WebPACK tool, the design features are supported.
Specification | Value |
---|---|
Programmable Type | In System Programmable |
Delay Time tpd(1) Max | 6.7ns |
Voltage Supply - Internal | 1.7V ~ 1.9V |
Number of Logic Elements/Blocks | 16 |
Number of Macrocells | 256 |
Number of Gates | 6000 |
Number of I/O | 173 |
Operating Temperature | -40℃ ~ 85℃ (TA) |
Mounting Type | Surface Mount |
Package / Case | 208-BFQFP |
Supplier Device Package | 208-PQFP (28x28) |
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