In a single CPLD, Xilinx XC2C64A-7CP56I combines the incredibly low power adaptability of the XPLA3 family with the high speed and simplicity of use associated with the XC9500/XL/XV CPLD family. This implies that, with the extra benefit of in-system programming, the exact same components can be used for high-speed data communications/computing systems and cutting-edge portable devices. One family that is simple to use and economical combines high-speed operation with low power consumption. The users' power budget is increased through clocking strategies and other power-saving measures. Starting with the Xilinx ISE 4.1i WebPACK tool, the design features are supported.
|In System Programmable
|Delay Time tpd(1) Max
|Voltage Supply - Internal
|1.7V ~ 1.9V
|Number of Logic Elements/Blocks
|Number of Macrocells
|Number of Gates
|Number of I/O
|-40℃ ~ 85℃ (TA)
|Package / Case
|Supplier Device Package
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