Without the use of "turbo bits" or other power-down techniques, the XCR22LV10-15SO24C is the first SPLD to combine great performance with low power. To accomplish this, Xilinx has adopted their FZP design process, which substitutes a cascaded chain of pure CMOS gates for conventional sense amplifier methods for implementing productterms (a technique that has been used in PLDs since the bipolar period).As a result, the PLDarena now has access to the hitherto unachievable combination of low power and high speed. The XCR22LV10-15SO24C from Xilinx is a 3V implementation that delivers fast speed and low power.
The XCR22LV10-15SO24C implements sum-of-products equations directly thanks to its use of the well-known AND/OR logic array structure. A fixed OR array is driven by a programmable AND array in this device. An "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback, receives the OR sum of products as its input.
The XCR22LV10-15SO24C implements logic functions using programmable-AND/fixed-OR logic arrays and assum-of-products expressions. Programming the connections of input signals into the array creates user-defined functions. I/O macrocells, user-configurable output structures, add even more flexibility to the logic.
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