XQR5VFX130-1CF1752B belonging to space-grade Virtex®-5QV FPGA offers RH by design technology, making it the only reprogrammable and most dense radiation-hardened (RH) FPGA available to suit the needs of space applications that demand both high performance and high reliability. System designers of high-performance space applications with lengthy development and manufacturing delays as well as expensive non-recurring engineering (NRE) expenses had no choice but to use ASICs for years. Without the high risk of ASICs, this XQR5VFX130-1CF1752B offers unmatched density, performance, and radiation proofing together with the adaptability of reconfigurability.
User-programmable gate arrays with embedded cores that are optimized for high-density and high-performance system designs are known as Virtex-5QV devices. Implemented by Virtex-5QV hardware are the following features:
• I/O blocks serve as the interface for the internal, reconfigurable logic and package pins. Programmable I/O blocks (IOBs) support the majority of common and cutting-edge I/O standards. For improved source-synchronous interface, the IOBs can be coupled to extremely flexible ChipSync logic. Per-bit deskew (on both input and output signals), data serializers/deserializers, clock dividers, and dedicated I/O and local clocking resources are examples of source-synchronous optimizations.
• The core logic components of Xilinx® FPGAs, Configurable Logic Blocks (CLBs), offer combinatorial and synchronous logic, distributed memory, and SRL32 shift register functionality. In comparison to earlier generations of programmable logic, Virtex-5QV FPGA CLBs offer better capabilities and performance because they are built on actual 6-input LUT technology.
• Block RAM modules offer cascadable 36 Kb genuine dual-port RAM that is versatile and may be used to create larger memory blocks. For better device use, Virtex-5QV FPGA block RAMs now come with optionally configurable FIFO logic.
For designs that require smaller RAM blocks, each block RAM can also be set up as two independent 18 Kb true dual-port RAM blocks.
The only reprogrammable RH FPGA in the industry
• Highest density RH FPGA
• Product intended for use in Space environment offered in full V-Grade and B-Grade manufacturing and screening
process flows
• The product grades are differentiated via the test flow process only
• High signal-integrity ceramic flip-chip column grid array packaging
• Best-in-class signal and power integrity performance levels achieved with chip capacitors mounted onto the FPGA
substrate connected to the VCCINT, VCCAUX, and VCCO power supply rails
• The same package substrate and chip capacitors are used in the assembly of the B-Grade and V-Grade products.
• Guaranteed operation over full military temperature range (–55°C to +125°C)
• Guaranteed 1 Mrad(Si) total ionizing dose per method 1019
• Guaranteed SEE latch-up immunity to LET >100 MeV per mg-cm2
• Radiation-Hardened By Design (RHBD) technology
• SEU Hardened Configuration Memory Cells and control logic
• Configuration Memory Orbital Upset Rate (GEO): 3.8E-10 errors/bit/day
• Configuration Control Logic Single-Event Functional Interrupt (SEFI) Orbital Upset Frequency (GEO): less than
once every 10,000 years
• SEU and SET Hardened CLB flip-flops
• SEU Hardened IOB flip-flops and DCI control
• Embedded error detection and correction (EDAC) and autonomous writeback for high-performance Block Memory SEU
Mitigation
• Fully characterized for space radiation effects in heavy ion and proton environments
Infotainment
Broadcast camera
Industrial motor control
Industrial networking
Machine vision
IP and Smart camera
Specification | Value |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
JESD-30 Code | S-CBGA-X1752 |
Number of CLBs | 10240 |
Number of Terminals | 1752 |
Operating Temperature-Min | -55.0 Cel |
Operating Temperature-Max | 125.0 Cel |
Organization | 10240 CLBS |
Package Body Material | CERAMIC, METAL-SEALED COFIRED |
Package Code | CGA |
Package Shape | SQUARE |
Package Style | GRID ARRAY |
Seated Height-Max | 9.6 mm |
Supply Voltage-Nom | 1.0 V |
Supply Voltage-Min | 0.95 V |
Supply Voltage-Max | 1.05 V |
Surface Mount | YES |
Technology | CMOS |
Temperature Grade | MILITARY |
Terminal Finish | TIN LEAD |
Terminal Form | UNSPECIFIED |
Terminal Pitch | 1.0 mm |
Terminal Position | BOTTOM |
Total Dose | 1M Rad(Si) |
Length | 45.0 mm |
Width | 45.0 mm |
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