The MACH 4 family from Lattice provides a superior Complex Programmable Logic Device (CPLD) solution of user-friendly silicon components and software tools. It also offers an unusually versatile architecture. A proven and predictable CPLD solution, a quicker time to market, more flexibility, and lower costs are the main advantages for users. The MACH 4 devices provide densities between 32 and 256 macrocells with 100% pin-out retention and 100% utilization.The MACH 4 family may operate at 3.3-V (M4LV-x8x) and 5-V (M4 xxx) voltages.Through the JTAG (IEEE Std.1149.1) interface, MACH 4 products can be in-system programmed at 5-V or 3.3-V. Additionally, JTAG boundary scan testing enables device connectivity testing on automated test equipment for products. Every member of the MACH 4 family offers First-Time-Fit, simple system integration, and pin-out retention following any design change or refit. MACH 4 devices can supply 111 MHz feNT through the and assured fixed timing as quickly as 75 ns for both 3.3-V and 5-V operation.When employing up to 20 product terms per output, the SpeedLocking feature is used.
FUNCTIONAL DESCRIPTION
The basic building blocks of MACH 4 devices are a number of enhanced PAL blocks coupled by a central switch matrix. The center switch matrix directs inputs to the PAL blocks and enables communication between the PAL blocks. Instead of needing to employ several devices, the logic designer can develop huge designs using just the core switch matrix and PAL blocks. The connecting protocols are crucial for effectively utilizing these devices. The output switch matrix and the logic allocator in the MACH 4 design provide flexible coupling of the macrocells to the product terms and the I/O pins to the macrocells. The input switch matrix also offers extra input routing choices. These resources offer the adaptability required to efficiently fit designs.
FEATURES
◆High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆Flexible architecture for rapid logic designs Excellent First-Time-Fit and refit feature
- - SpeedLocking performance for guar anteed fixed timing Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆High speed
-7.5ns tpp Commercial and 10ns tpp Industrial
111.1MHz fcNτ
◆32 to 256 macrocells; 32 to 384 registers
◆44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆Flexible architecture for a wide range of design styles D/T registers and latches,
- Synchronous or asynchronous mode Dedicated input registers
- Programmable polarity Reset/ preset swapping
◆Advanced capabilities for easy system integration
3.3-V & 5-V JEDEC-compliant operations
- JTAG (IEEE 1149.1) compliant for boundary scan testing
3.3-V & 5-V JTAG in-system programming
- PCI compliant (-71- 10/-12 speed grades)
Safe for mixed supply voltage system designs
Bus-FriendlyTM inputs and 1Os
Programmable' security bit
Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Supported by ispDesignEXPERTM software for rapid logic development
- - Supports HDL design methodologies with results optimized for MACH 4
- Flexibility to adapt to user requirements
Software partnerships that ensure customer success
◆Lattice and third-party hardware programming support
- LatticePROTM software for in-system programmability support on PCs and automated test equipment
Programming support on all major programmers including Data l/O, BP Microsystems, Advin,and System General
