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MAX 7000 CPLD Overview

High-density, high-performance PLDs in the MAX 7000 CPLD family are based on Altera's second-generation MAX architecture. The EEPROM-based MAX 7000 family is constructed using cutting-edge CMOS technology and offers counter speeds of up to 175.4 MHz, ISP, pin-to-pin delays as little as 5 ns, and 600 to 5,000 useable gates. The PCI Special Interest is met by MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in the -5, -6, -7, -10P, and -12P speed grades.

The EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices are part of the MAX 7000E device family. These devices include a number of improved features, including more global clocking, additional output enable controls, improved interconnect resources, fast input registers, and a programmable slew rate.

The MAX 7000S devices, also known as the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices, are in-system programmable MAX 7000 components. In addition to JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option, MAX 7000S devices have the improved features of MAX 7000E devices.

MAX 7000 CPLD Devices

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