AGLP125V5-CSG281

AGLP125V5-CSG281 Overview

Based on a 130 nm flash processing technology, the AGLP125V5-CSG281 provides the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and a wealth of advanced capabilities.

It is possible to enter and exit an ultralow-power mode that uses as little as 5 W while preserving the design data, SRAM content, registers, and I/O states thanks to the Flash*Freeze technology utilized in AGLP125V5-CSG281. With its quick return to operating mode and simplified I/O and clock management, Flash*Freeze technology streamlines power management. The AGLP125V5-CSG281 can be used in the system with full functionality while using extremely little power thanks to the Low Power Active capabilities (static idle). As a result, the AGLP125V5-CSG281 may manage the system's power consumption based on external inputs (such as searching for keyboard stimuli).

AGLP125V5-CSG281 benefits from nonvolatile flash technology by being a safe, low-power, single-chip solution that is life at power-up (LAPU). AGLP125V5-CSG281 is reprogrammable and provides advantages in time to market at an ASIC-level unit price.

These properties make it possible for designers to use current ASIC or FPGA design flows and tools to produce high-density systems.

AGLP125V5-CSG281 has clock conditioning circuitry based on an integrated phase-locked loop (PLL), as well as 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage. IGLOO PLUS devices provide up to 212 user I/Os, up to 36 kbits of real dual-port SRAM, and up to 125 k system gates. The AGLP125V5-CSG281 doesn't support PLL or RAM.

AGLP125V5-CSG281 Specifications