5SGSMD4H2F35I2L features up to 66 full-duplex transceiver channels, with transceivers at data rates from 14.1 Gbps to 28.05 Gbps. Providing up to over 930 Gbps of transceiver bandwidth, 5SGSMD4H2F35I2L delivers the highest system bandwidth at the lowest power consumption for a wide range of applications and protocols. In addition, the transceivers are compliant with a range of protocols and are equipped with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip applications.
5SGSMD4H2F35I2L transceivers also include full-featured embedded physical coding sublayer (PCS) hard intellectual property (IP) to simplify design, lower power, and save valuable core resources. The 5SGSMD4H2F35I2L transceiver channel consists of the physical media attachment (PMA), PCS, and hardened IP blocks with added clocking flexibility and more independent channels. Each channel has a full PMA and PCS along with a dedicated, independent receive analog PLL CDR. You'll have access to an abundant number of transmit clocking sources, including the wide data range support of the clock multiplication unit (CMU) as well as the low-jitter LC transmit PLLs. Plus, you can minimize the number of off-chip crystal oscillators by utilizing the new fractional PLLs with precise frequency synthesis. Not only can the fractional PLLs generate fractional multiples of a reference clock, they can also be used to drive the transceiver reference clock.
|Series||Stratix V GS|
|Number of Logic Blocks||957|
|Number of I/Os||432|
|Maximum Operating Temperature||+ 85℃|
|Package / Case||FBGA-1152|
|Distributed RAM||19 Mbit|
|Minimum Operating Temperature||- 40℃|
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